GPS/GSM/GPRS modem Watchdog monitor. GSM modem watchdog timer, the application to watch the status of the satellite modem. Based on ATtiny13V microcontroller. Also contains an power supply (LM5576 or LM25576 IC) and battery charger (LTC4054) circuits.

Schematic diagram. Click to enlarge.



Watchdog Monitor PCAD2006 Schematic file. Click to download.

Computer interface Schematic diagram. Click to enlarge.



Computer interface PCAD2006 Schematic file. Click to download.

Source code (IAR Embedded Workbench):

#include "iotiny13.h"
#include <inavr.h>

#define bit(n) (1 << (n))
#define setbit(p,n) (p|=bit(n))
#define clrbit(p,n) (p&=~bit(n))
#define invbit(p,n) (p=p^bit(n))
#define tstbit(p,n) (p&bit(n))

#define MasterClock 9600000

#define delay_us(c) __delay_cycles(MasterClock/1000000*c)
#define delay_ms(c) __delay_cycles(MasterClock/1000*c)


volatile unsigned int SecondCounter = 0;

#pragma vector = INT0_vect
__interrupt void INT0_vect_Interrupt(void)
{

    SecondCounter = 0; // Interrupt from GSM module
}//INT0_vect_Interrupt

void main (void)
{

    PORTB = 0x00; // Port B init
    DDRB = 0x02;

    CLKPR = 0x80; // Prescaler = 1
    CLKPR = 0x00;

    GIMSK = 0x40; // INT0 on
    MCUCR = 0x01;

    GIFR = 0x40;

    GIMSK=0x60;
    MCUCR=0x01;

    PCMSK=0x04;
    GIFR=0x60;

    WDTCR = 0x39; // Watchdog Timer Prescaler: OSC/1024k

    WDTCR = 0x29;

    asm ("sei"); // Interrupts enabled

    // GSM module on sequence

    setbit(PORTB, 1); // ON = 1
    delay_ms(1000); // Wait 1 second

    __watchdog_reset(); // WatchDog reset
    clrbit(PORTB, 1); // ON = 0
    delay_ms(2000); // Wait 2 seconds

    __watchdog_reset(); // WatchDog reset
    setbit(PORTB, 1); // ON = 1

    while (1)
    {

        delay_ms(1000); // Wait 1 second
        SecondCounter++;
        __watchdog_reset(); // WatchDog reset
        if (SecondCounter > 3600) // Fault condition

        {
            // Try to reload
            setbit(PORTB, 1); // ON = 1
            delay_ms(1000); // Wait 1 second

            __watchdog_reset(); // WatchDog reset
            clrbit(PORTB, 1); // ON = 0
            delay_ms(2000); // Wait 2 seconds

            __watchdog_reset(); // WatchDog reset
            setbit(PORTB, 1); // ON = 1

            SecondCounter = 0; // Zeroing

        }
    }
}